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| ? motorola, inc., 2003 AN2140/d rev. 1, 6/2003 serial monitor for mc9s08gb/gt application note by jim sibigtroth 8/16 bit systems/applications engineering austin, texas introduction this application note describes a 1-kbyte monitor program for the mc9s08gb60 mcu. this program supports 19 primitive debug commands to allow flash programming and debug through an rs-232 serial interface to a personal computer. this monitor supports primitive commands to reset the target mcu, read or modify memory (including flash memory), read or modify cpu registers, go, halt, or trace single instructions. in order to allow a user to specify the address of each interrupt service routine, this monitor enables a hardware logic feature that redirects interrupt vectors to an unprotected portion of flash just before the protected monitor program. this monitor will be modified for use with other members of the hcs08 family as they are introduced. a user on a tight budget can evaluate the mcu by writing programs, programming them into the mcu, and debugging their applications for the hcs08 using only a serial i/o cable and free software for their personal computer. this monitor does not use any ram other than the stack itself. the monitor turns off the cop watchdog. this development environment assumes you reset to the monitor when you are going to perform debug operations. if your code takes control directly from reset, and then an sci1 interrupt or software interrupt (swi) attempts to enter the monitor, the monitor may not function because the sci, frequency-locked loop (fll), fclk, and cop may not be initialized as they would be for a cold reset into the monitor. there is limited error handling for the fll. if the frequency source is missing or broken, the monitor will not function. the crystal oscillator can take any amount of time to start. if the fll loses clocks after the monitor is running, a reset is forced. if the fll loses lock during operation, it may or may not fail ? if it can regain lock, it can continue normally. if a user interrupt service routine (isr) is present, the monitor uses that routine. if there is no user isr, the monitor icg f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
AN2140/d 2 serial monitor for mc9s08gb/gt isr acknowledges the error and does a real-time interrupt (rti). if the loss of lock was due to noise, the monitor would resume normal operation. if there was a more serious problem such as a broken fll, the monitor would stop working. normally, interrupts are blocked while the monitor has control so this isr is really just included for the case where a user clears i in their code and then the icg experiences a loss of lock. (this reduces the risk that an icg failure would lock up the user?s application.) block protection in order to prevent accidental changes to the monitor program itself, the 1 kbyte block of flash memory where it resides ($fc00?$ffff), is block protected. the only way to change the contents of this protected block, is to use a bdm-based development tool (a bdm pod) to disable the block protection and then bulk erase the flash memory (or at least the last two 512-byte pages). in the lowest-cost applications where the monitor is used with an sci serial interface to the rs-232 serial port on a personal computer, there is no way to accidentally erase or modify the monitor software. not even errors in a user program can cause changes to the monitor because the block protect can only be disengaged through a bdm command with a bdm-based debug pod. baud rate detection the mc9s08gb60 version of this monitor assumes a 32.768-khz crystal. it programs the fll to produce a bus frequency of 18.874368 mhz and accommodates rs-232 serial communications through sci1 at 115.2 kbaud. the monitor does not attempt to allow debugging of a user program that uses a different crystal frequency or sets up the fll differently. for such systems, you should purchase a bdm pod which allows more sophisticated debugging. other variations of the monitor will use the internal oscillator on some hcs08 derivatives and/or other combinations of crystals and fll settings. however, they will all send a break and wait for a carriage return before sending the first prompt sequence. in a later section of this application note, the parameters and control register settings that are related to the oscillator, fll, and other frequency-sensitive features of the monitor will be discussed in greater detail. during initialization after any cold reset, a long break is transmitted before other sci communications. this break is about 30 bit-times to ensure that a windows-based pc can recognize this as a break. in order to establish communications with the monitor, the host must send a carriage return ($0d) at the correct baud rate. if the monitor detects some other character, it implies f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d monitor commands serial monitor for mc9s08gb/gt 3 the host baud rate is not correct so it continues to wait in a loop for the $0d character before printing the first prompt sequence. the host can detect the monitor baud rate by initially sending a carriage return at 115.2 kbaud. if this is the correct baud rate, the target mcu will respond with a prompt sequence of $e0, $08, and a ">" prompt character. if the host does not see the prompt sequence, it should try sending another carriage return at 57.6 kbaud, then 38.4 kbaud, then 19.2 kbaud, and finally 9600 baud, until the prompt sequence is received to indicate the correct communication rate. monitor commands the monitor recognizes 19 primitive binary commands that enable a third-party development tool vendor to develop a full-featured debug program. these commands use 8-bit command codes optionally followed by binary addresses, control, and data information depending upon the specific command. in the following command descriptions, a shorthand notation is used to describe the command syntax. each command starts with a binary command code. a slash (/) is used to separate parts of the command in these descriptions, but these slash characters are not sent as serial characters in commands. underlined parts of the command are transmitted from the host pc to the target mcu while the portions that are not underlined are transmitted from the target mcu to the host pc. the first two characters in each command sequence are the 1-byte command codes and are shown as a literal hexadecimal value such as a1. other abbreviations used in the command sequences are shown here: aa ? the contents of the 8-bit accumulator aaaa ? a 16-bit address cc ? the contents of the 8-bit condition codes register eadr ? the 16-bit end address for an erase command hh ? the contents of the 8-bit h register (high half of h:x) nn ? the number of bytes (?1) for the block read and write commands ph ? the upper 8-bits of the user?s program counter (pch) pl ? the lower 8-bits of the user?s program counter (pcl) rd ? one byte of read data rd (aaaa) /rd (aaaa+1) /.../rd (aaaa+nn) ? a series of 8-bit read data values from address locations aaaa through aaaa+nn. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 4 serial monitor for mc9s08gb/gt sadr ? the 16-bit start address for an erase command sh ? the upper 8-bits of the user?s stack pointer (sph) sl ? the lower 8-bits of the user?s stack pointer (spl) wd ? one byte of write data wd (aaaa) /wd (aaaa+1) /.../wd (aaaa+nn) ? a series of 8-bit write data values for address locations aaaa through aaaa+nn. xx ? the contents of the 8-bit index register x (low half of h:x) some monitor commands such as read_byte and write_byte can be executed at any time while others may only be executed while the monitor is active and waiting for commands (as opposed to running user code). commands such as those that write to cpu registers would not make sense while user code is running because they would result in unexpected program execution. if these commands are attempted while user code is running, the command will not be executed and an error message will be returned to the host system as part of the next prompt sequence. unless otherwise noted in the following command descriptions, the command can be executed at any time (while the monitor is active or while a user program is running). $a1 ? read_byte a1 /aaaa /rd ? reads a byte of data from the specified 16-bit address and sends the 8-bit data back to the host pc. $a2 ? write_byte a2 /aaaa /wd ? writes the supplied byte of data to the specified 16-bit address. all writes are processed through an intelligent routine that programs flash or writes to ram or registers based on the address being written. if any error occurs during an attempt to program a nonvolatile memory location, an error code is transmitted before a new prompt is issued. see intelligent writes for more detail. $a5 ? read_next a5 /rd ? pre-increments the user h:x register (by 1), reads the byte of data from 0,x, and sends the 8-bit data back to the host pc. this command is not allowed when the user program is running because the monitor cannot control the contents of the h:x index register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d monitor commands serial monitor for mc9s08gb/gt 5 $a6 ? write_next a6 /wd ? pre-increments the user h:x register (by 1) and writes the supplied byte of data to 0,x. all writes are processed through an intelligent routine that programs flash or writes to ram or registers based on the address being written. if any error occurs during an attempt to program a nonvolatile memory location, an error code is transmitted before a new prompt is issued. see intelligent writes for more detail. this command is not allowed when the user program is running. $a7 ? read_block a7 /aaaa /nn /rd (aaaa) /rd (aaaa+1) /.../rd (aaaa+nn) ? reads a series of nn+1 (1 to 256) bytes of data starting at address aaaa and returns the data one byte at a time to the host (starting with the data read from address aaaa and ending with the data from address aaaa+nn). although this command can be executed while a user program is running, it is not usually recommended because it could slow down operation of the user program. $a8 ? write_block a8 /aaaa /nn /wd (aaaa) /wd (aaaa+1) /.../wd (aaaa+nn) ? writes a series of nn+1 (1 to 256) bytes of data into the target mcu?s memory starting at address aaaa and ending with address aaaa+nn. all writes are processed through an intelligent routine that programs flash or writes to ram or registers based on the address being written. if any error occurs during an attempt to program a nonvolatile memory location, an error code is transmitted before a new prompt is issued. see intelligent writes for more detail. this command is capable of programming locations in flash memory even while a user program is running from within the same flash memory. although this command can be executed while a user program is running, it is not usually recommended because it could slow down operation of the user program. $a9 ? read_regs a9 /sh/sl/ph/pl/hh/xx/cc/aa ? sends the current contents of user registers sph, spl, pch, pcl, h, x, ccr, a (in that order) to the host pc. the sp value is the user sp value and while the monitor is active and waiting for commands, the real sp is 6 less due to the user register stack frame. although this command can be executed while a user program is running, it is not usually recommended because these register values change much more quickly than they can be read. $aa ? write_sp aa /sh /sl ? adjusts the specified 16-bit data to compensate for the user register stack frame (?6) and writes this adjusted value to the stack pointer register. the monitor uses stack space below the user register stack frame. when you execute a go or trace1 command, the monitor exits to the user program by pulling h and then executing an rti instruction. because of the monitor requirements for stack space, the valid range of values for sp in the write_sp command is from ramstart+$45 to ramlast. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 6 serial monitor for mc9s08gb/gt the monitor doesn?t move the user register values to the new user register stack frame so the host should re-write all user register values after changing the sp value, and before attempting to display current user register values. this command is not allowed when the user program is running. the first aa in this command sequence is the write_sp command code. $ab ? write_pc ab /ph /pl ? writes the specified 16-bit data to pch:pcl in the user register stack frame. this command is not allowed when the user program is running. $ad ? write_hx ad /hh /xx ? writes the specified 16-bit data to the h:x index register pair in the user register stack frame. this command is not allowed when the user program is running. $ae ? write_a ae /aa ? writes the specified 8-bit data to accumulator a in the user register stack frame. this command is not allowed when the user program is running. $af ? write_ccr af /cc ? writes the specified 8-bit data to the condition codes register (ccr) in the user register stack frame. this command is not allowed when the user program is running. $b1 ? go b1 ? the monitor pulls h then executes an rti to copy user cpu register values from user register stack frame into the actual cpu registers. processing resumes in the user program at the location specified by the user program counter that was in the user register stack frame. to go to an arbitrary address in the user?s program, you can first use a write_pc command to set the user?s program counter to a new location. in run mode, the user?s application program will execute until it is interrupted by a breakpoint, an sci1 interrupt, or a halt command. in the case of a breakpoint or halt command, the monitor will clear the run mode flag to indicate to the monitor that it should remain active waiting for further commands from the host. in the case of an sci1 interrupt, the run flag is set (or remains set) to indicate that the monitor should return to the user?s application program after completing the current command. since the monitor requires the swi and sci1 interrupt vectors to be programmed with specific values, the go and trace1 commands perform a check to make sure these vectors are good before exiting the monitor to run user code. if the vector locations are erased ($ff), the verification routine tries to program the correct values into the flash vector locations. if this is successful, or if the vectors were already correct, the monitor finishes with a go or trace1 command. if the vectors cannot be programmed correctly, the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d monitor commands serial monitor for mc9s08gb/gt 7 monitor aborts the go or trace1 command and reports the error with the next prompt sequence. if the go command is executed while a user program is running, control returns to the running user program. $b2 ? trace1 b2 ? the monitor sets up the on-chip debug module to force a cpu breakpoint immediately after executing a single instruction in the user?s program. it then pulls the h register and executes an rti to copy user cpu register values from user register stack frame into the actual cpu registers. processing resumes in the user program at the location specified by the user program counter that was in the user register stack frame. after executing a single user instruction, an swi is forced to cause control to return to the monitor program. in response to the swi, the monitor clears the run flag (or leaves it cleared) to indicate that the monitor should remain active waiting for additional commands from the host. since the monitor requires the swi and sci1 interrupt vectors to be programmed with specific values, the go and trace1 commands perform a check to make sure these vectors are good before exiting the monitor to run user code. if the vector locations are erased ($ff), the verification routine tries to program the correct values into the flash vector locations. if this is successful, or if the vectors were already correct, the monitor finishes with a go or trace1 command. if the vectors cannot be programmed correctly, the monitor aborts the go or trace1 command and reports the error with the next prompt sequence. if the trace1 command is executed while a user program is running, one additional user program instruction will be executed and then the monitor will become active and wait for additional commands. $b3 ? halt b3 ? this command is used to force the user?s application program to stop executing and the monitor to gain control and remain active to wait for additional commands from the host. this command requires an enabled sci1 interrupt so it can only be recognized if the user application program has cleared the i bit in the ccr. if the user program temporarily blocks interrupts, such as during execution of another interrupt service routine, the halt command will not be recognized until the user application program re-enables interrupts (typically by executing the rti at the end of an interrupt service routine). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 8 serial monitor for mc9s08gb/gt $b4 ? reset b4 ? if there is a programmed user reset vector, the level on the user/monitor switch (pta7 in the mc9s08gb60), and the level on the rxd1 line; this will cause a reset to user code or to the monitor. the sequence of checks at reset include: 1. check for possible stop2 mode recovery (indicated when the ppdf bit in spmsc2 register is 1). if ppdf = 1, the mcu pins remain latched to the states whey had when stop2 mode was entered. control is passed to the user?s reset initialization code so pin and peripheral states can be reconfigured before ppdack is written to restore i/o pins to normal operation. 2. check for warm start (which implies reset was caused by an sci1 rx interrupt or a break in the user code (swi) where the sp was not valid in the interrupt service routine.) a warm start is indicated when all of the following conditions are true... a. srs register indicates reset was caused by an illegal opcode b. a 16-bit signature at ramlast ? 3 = warmsig c. the old saved baud rate at ramlast matches the normal baud rate setting for the monitor (baud115200 in the mc9s08gb60) warm start skips the long break and restores the previous baud rate instead of waiting for the next carriage return. the warm reset is needed in the case of an sci1 rx interrupt or swi with an invalid sp value because the interrupt stacking could have corrupted ram or register values and because the monitor cannot function without a valid stack. 3. if the user/monitor switch (pta7 in the mc9s08gb60) = 0 (logic low), force monitor reset 4. if rxd1 = 0 (logic low) force monitor reset. if no rs-232 device is connected, or if rxd is being driven by an idle level, rxd1 will be 1 so monitor mode is not selected. 5. if the first byte of the user reset pseudo-vector = $ff (unprogrammed) force monitor reset if none of the above, use the reset pseudo-vector to jump to the user?s reset startup routine. two pullup enable registers are modified during the monitor startup, but they are restored to their reset values before going to the user reset location. the user has complete control over all control registers (including write-once registers and bits) as if the user's reset routine had started immediately after the actual reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d command error codes serial monitor for mc9s08gb/gt 9 $b5 ? erase b5 /sadr /eadr ? erase pages of flash memory starting with the flash page that includes address sadr and ending with the flash page that includes address eadr. sadr and eadr must specify a valid range of addresses in flash memory. before checking for a valid flash address range (in the mc9s08gb60), the low order half of sadr is forced to $80 and the low order half of eadr is forced to $ff. multi-page erase commands are accomplished by starting with a page address of sadr (after modification) and repeating a loop that erases one page of flash memory, adds $200 (512) to the page address, and repeats the loop until the page address is past the address eadr (after modification). this unusual algorithm prevents any possibility of unintended changes to high-page registers in case the range of flash addresses being erased overlaps the high-page register space from $1800?$182b and prevents the possibility that the starting address would fall in the inaccessible portion of the first flash page ($1000?$107f) where internal ram takes priority over the flash memory. $b6 ? erase_all b6 ? erase all flash memory except the 1-kbyte monitor at $fc00?$ffff. if this command is issued while an application program is running, the run flag is cleared so the monitor retains control after the flash memory is erased. $b7 ? device_info b7 ? returns the hcs08 device revision and id code followed by a normal prompt sequence. in hcs08 devices, the information for the mask revision and device id comes from the system device identification register (sdidh:sdidl) at $1806:$1807 which contains a 4-bit revision number and a 12-bit device identification code. for the original mc9s08gb60, this code is $0:$002, so the complete response to the $b7 device_info command is: $00, $02, $e0, $00 (or $01 if a user program is running), $3e (the prompt symbol ?>?). command error codes a 3-character prompt is issued after monitor initialization and after each command is completed. a prompt is not issued after a go command until a breakpoint is encountered or a halt command stops execution of the user?s application program. the prompt sequence consists of a 1-byte error code, a 1-byte status code, and a ?>? prompt symbol ($3e). after initialization or after a command is executed successfully, the error code is $e0 indicating no error. after a cold reset initialization, the status code is $08 indicating a hard reset has occurred and the monitor is in active monitor mode waiting for additional commands from the host. therefore the complete 3-character prompt after a cold reset is $e0, $08, $3e. some commands are not allowed while the target mcu is in run mode because they would interfere with proper execution of the application program (see error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 10 serial monitor for mc9s08gb/gt code $e2). in addition, other commands are not recommended while the target mcu is in run mode, but since these commands do not interfere with proper execution of the application program, other than to slow it down, they are allowed to execute and do not result in an error. the following paragraphs describe each of the possible error codes in more detail. $e0 ? no error this code is used after any successful command. it indicates there are no pending errors. $e1 ? command not recognized this code indicates the previous command code was not one of the recognized command codes. if the monitor was in run mode, control returns to the user?s application program. if the monitor was not in run mode, control returns to the top of the command loop to wait for the next command from the host. $e2 ? command not allowed in run mode this code indicates that the requested command is only legal when the monitor is halted (active monitor mode). in the case of a command request that is not legal in run mode, the command is not executed to avoid corrupting the running user application program. the commands that are not allowed in run mode are: read_next and write_next are not allowed because these commands use the user?s h:x register value as a pointer and this value constantly changes during run mode. write_sp, write_pc, write_hx, write_a, and write_ccr are not allowed in run mode because they change much faster than the host could check their contents. therefore there is no way to predict how these changes would affect the application program so it would not make sense to execute these commands while the application program is running. although commands that write to memory or erase flash memory (write_byte, write_block, erase, or erase_all) are allowed while running a user program, care should be used to avoid changing the program itself while it is executing. $e3 ? stack pointer out of range this error code indicates that when the monitor program took over control from a running user program, the stack pointer was not pointing to a valid ram location. this is an unrecoverable error because the interrupt that caused the monitor to gain control wrote to several memory locations above the current invalid stack pointer location. if the stack pointer was pointing into the on-chip registers, this could have corrupted important system configuration settings. in addition, the user pc value may not have been written to a read/write location so the monitor would not know where to return to the user program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d command error codes serial monitor for mc9s08gb/gt 11 since the monitor requires certain control register settings and a valid stack to function correctly, a bad sp error results in the monitor forcing a reset to restore required settings. most of the time, this can be a warm reset that skips the long break and the checks for going directly to the user reset vector. after the warm reset, clocks and control registers are initialized and the prompt will include the bad sp error message and the warm start status code ($e3, $0c, $3e). a warm reset is also forced if the monitor gets an unexpected interrupt from the sci1 tx or error interrupt sources. if the user program has experienced code runaway and has changed the sci1 control registers to allow these interrupts, the safest response is to force a (warm) reset to allow the monitor to regain control. $e4 ? write_sp attempted with an invalid sp value this error code indicates that the host attempted a write_sp command with an invalid 16-bit sp value. in order for the monitor program to function correctly, the sp must always point into a valid area of ram to support monitor functions. the write_sp command adjusts the supplied sp value (by subtracting 6) to compensate for the user register stack frame. in addition the monitor needs a certain amount of stack space for stacking return addresses for nested subroutine calls and for temporary storage of register contents during the normal course of executing the monitor program. because of these monitor requirements, the valid range of values for sp is a little less that the whole range of ram addresses. see $aa ? write_sp for more detail. $e6 ? flash error this code indicates that an error occurred during an attempt to write or erase flash memory. possible errors that would trigger this error code are: an faccerr (access error) an fpviol (protection violation error) an attempt was made to program a flash location that was not previously erased in cases where a single byte was being programmed or a single page was being erased, the attempted flash operation would not be performed. in cases where multiple bytes were being programmed or multiple pages were being erased, this error indicates that at least one location or page erase operation was not performed. this monitor does not provide more detailed information about these errors. the debug tool or programmer running in the host pc can perform additional memory reads to get more detailed information about the error. $e7 ? erase range error the flash memory in an hcs08 is organized into pages of 512 bytes each. the starting address sadr and the ending address eadr for the erase command must specify a valid range of addresses in the flash memory or f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 12 serial monitor for mc9s08gb/gt this $e7 error will be generated and no flash locations will be erased. refer to $b5 ? erase for more information. $e8 ? go or trace1 with no vectors this code indicates that a go or trace1 command was attempted, but critical interrupt vectors for swi or sci1 were not properly initialized in the unprotected area of flash memory at $fbxx. if possible, the monitor will try to program correct vectors into these locations. however, if the locations contained non-ff values, programming is not possible to fix the vectors without erasing user flash memory. monitor status codes the second character of a 3-character prompt is a status code that tells the host debug program the current state of the monitor. $00 ? monitor active this code indicates that the user?s application program is not currently running and the monitor is active and waiting for further commands from the host. $01 ? user program running this code indicates that the user?s application program is currently running. in this mode, the host may still issue commands to read or write memory locations or halt the user program so the monitor regains control. however, the monitor can only honor such command requests if/when the user program has cleared the i bit in the ccr because these commands rely on an sci1 receive interrupt to gain the attention of the monitor program. $02 ? halt this code indicates that a halt command was executed to stop the running user program. after the halt command, the monitor remains active waiting for additional commands. $04 ? trace done a trace1 command was just executed and the monitor is active waiting for additional commands. $06 ? breakpoint an swi was encountered and a trace1 command was not the cause of the swi. other possible causes of the swi include a breakpoint or the end of a debug run (both caused by the on-chip dbg module hardware). $08 ? cold reset this code indicates a cold reset has just occurred. the usual causes of cold reset are a power-on event, a reset command, or the user pressing the reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d command decode serial monitor for mc9s08gb/gt 13 button on the target system. a cold reset can also result if errors in a user program cause code runaway. in the case of code runaway, an attempt to execute an illegal opcode would generate a system reset. $0c ? warm reset this code indicates a warm reset has just occurred. the monitor makes a distinction between a cold reset and a warm reset in order to allow faster recovery when the reset is caused by a known event such as an swi or sci1 rx interrupt where the stack pointer was out of range. a warm reset can also be caused by an unexpected interrupt from the sci1 tx or error systems whether the stack pointer is good or not. although the stack pointer may be valid, an error must have occurred because these interrupts should never occur unless a user program disturbed the sci1 control settings. command decode the code in lines 517 through 528 implements a simple lookup table to decode monitor commands. the key to this routine is the command table which consists of a 3-byte entrsy for each command. the first byte of each entry is the command code such as $a1 for the read_byte command. the last two bytes of each entry are the high and low halves of the address where the command routine can be called. for example the 3-byte entry for the read_byte command is $a1,$fc06 in lines 227 and 266. the $a1 is the command code, and $fc06 is where the read_byte command routine (rdbytecmd) is located. lines 264 and 265 are the command table entries for the device_info command. the label tableend in line 266 marks the end of the command table. this structure makes it easy to add or remove commands. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 14 serial monitor for mc9s08gb/gt 227 fc06 a1 commandtbl: dc.b $a1 228 fc07 fd7a dc.w rdbytecmd ;read byte 229 230 fc09 a2 dc.b $a2 231 fc0a fda2 dc.w wtbytecmd ;write byte " " " " " " 264 fc3c b7 dc.b $b7 265 fc3d fd27 dc.w devicecmd ;return device information 266 0000 fc3f tableend: equ * ;end of command table marker " " " " " " " 517 fd5d ad 6c prompt1: bsr getchar ;get command code character 518 fd5f 45 fc06 ldhx #commandtbl ;point at first command entry 519 fd62 f1 cmdloop: cmp ,x ;does command match table entry? 520 fd63 27 0b beq doit ;branch if command found 521 fd65 af 03 aix #3 ;advance to next table entry 522 fd67 65 fc3f cphx #tableend ;see if past end of table 523 fd6a 26 f6 bne cmdloop ;if not, try next entry 524 fd6c a6 e1 lda #errcmnd ;code for unrecognized command 525 fd6e 20 d8 bra prompt ;back to prompt; command error 526 527 fd70 9ece 01 doit: ldhx 1,x ;get pointer to command routine 528 fd73 fc jmp ,x ;go process command monitor versus run mode the target mcu operates in either monitor active mode or run mode. monitor active mode refers to the mode of operation where the target mcu is executing code within the monitor and keeps active control waiting for additional commands through the serial interface. run mode refers to the mode of operation where the target mcu is executing the user?s application program. some monitor commands such as read_byte and write_byte can be executed while the target mcu is in run mode. in this case, an sci1 interrupt causes the monitor to temporarily gain control to decode and execute the requested command, but when the command is completed the monitor automatically returns control to the user?s application program. throughout such a sequence, the target mcu is said to be in run mode even though software in the monitor is executed to complete the requested command. the halt command causes an sci1 interrupt which causes the cpu registers (except h) to be pushed onto the stack. the isr for sci1 then sets the run mode flag (even though this flag will be cleared again if the command that caused the sci1 interrupt turns out to be the halt command). the h register is pushed to complete the user register stack frame, and the monitor proceeds to the command decode routine. breakpoints use the swi interrupt mechanism (the trace1 command also uses a hardware breakpoint), which is not blocked when the i bit in the ccr is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d intelligent writes serial monitor for mc9s08gb/gt 15 this implies that trace1 and breakpoints always work independent of what the user program does to the i bit. other commands use the sci1 interrupt, therefore these other commands cannot execute unless the user program clears the i bit. there are some cases where it would be natural for a user program to set the i bit (or leave it set) such as during reset initialization routines and when the user program is executing an interrupt service routine. most such cases would only block interrupts for a very short period of time so the user would not notice that a command request was delayed. if a user program erroneously fails to clear the i bit or gets stuck in an interrupt service routine, commands through the sci serial link cannot be recognized. if this condition persists, the user must force a reset or cycle the power to the target system so it gets a power-on reset so the monitor can regain control. intelligent writes the intelligent write routine uses the address in h:x to decide what to do. if the location is in flash, it checks to see if the location is already correct (if so it skips the program operation and signals success). if the flash location is different than desired, the routine checks to see if it is erased (it is considered an error if you try to change a location in nonvolatile memory that is not blank). if those checks pass, the routine does a byte program operation and finally checks faccerr and fpviol to make sure there was no access error or protection violation during programming (it is considered an error if there was). if the location is not flash, the routine writes the requested data to the specified address. see writea2hx subroutine and listing lines 1055?1088 for more detail. doonstack subroutine this unusual subroutine is used to program flash locations or perform page-erase operations in the flash memory. like most nonvolatile memories, you cannot execute a program out of the flash while a program or erase operation is being performed on the same nonvolatile memory. because of this, the doonstack subroutine (which is located in the flash), copies a small routine onto the stack (in ram) and then passes control to that subroutine on the stack. when the operation is finished, an rts returns control to the doonstack routine which deallocates the space used by the small stack routine and then returns to the program from where doonstack was called. prior to calling doonstack, the main program started a flash operation by writing to fstat to clear out any previous error flags. also, the a accumulator is pre-loaded with the command code for byte_prog or page_erase. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 16 serial monitor for mc9s08gb/gt the first two lines in doonstack save h and x on the stack, and the third line stores the command code on the stack. lines 1140 through 1144 copy the spsub routine onto the stack (with a series of psha instructions) starting with the last byte of spsub and ending with the push of the first byte of spsub onto the stack. at this point sp points to the location just before the first byte of the stacked spsub routine. the tsx in line 1145 copies sp+1 into h:x so h:x points at the copy of spsub on the stack. while the monitor program is active, the i bit in the ccr is set to mask interrupts. since this routine can also be called as a utility subroutine from a user program, the i bit may or may not be set at the time doonstack is called. lines 1146?1148 check to see if i is set or clear. if the i bit was already set, lines 1154?1155 load the data for the command and call the subroutine on the stack to complete the requested flash operation. if the i bit was clear, line 1149 is used to set i before calling the subroutine on the stack and line 1152 is used to restore it to 0 to re-enable interrupts when the flash memory is back in the map. line 1150 or 1154 preloads a with the data for the flash operation. the jsr in line 1151 or 1155 calls the copy of spsub that is now located on the stack. the spsub subroutine was written in a position-independent manner so it could be copied to a new location (on the stack) and would still execute as expected. in this case, spsub is such a short subroutine that it was easy to make it position independent. 1136 ff72 89 doonstack: pshx 1137 ff73 8b pshh ;save pointer to flash 1138 ff74 87 psha ;save command on stack 1139 ff75 45 ffb0 ldhx #spsubend ;point at last byte to move to stack 1140 ff78 f6 spmoveloop: lda ,x ;read from flash 1141 ff79 87 psha ;move onto stack 1142 ff7a af ff aix #-1 ;next byte to move 1143 ff7c 65 ff98 cphx #spsub-1 ;past end? 1144 ff7f 26 f7 bne spmoveloop ;loop till whole sub on stack 1145 ff81 95 tsx ;point to sub on stack 1146 ff82 85 tpa ;move ccr to a for testing 1147 ff83 a4 08 and #$08 ;check the i mask 1148 ff85 26 09 bne i_set ;skip if i already set 1149 ff87 9b sei ;block interrupts while flash busy 1150 ff88 9ed6 001e lda spsubsize+6,sp ;preload data for command 1151 ff8c fd jsr ,x ;execute the sub on the stack 1152 ff8d 9a cli ;ok to clear i mask now 1153 ff8e 20 05 bra i_cont ;continue to stack de-allocation 1154 ff90 9ed6 001e i_set: lda spsubsize+6,sp ;preload data for command 1155 ff94 fd jsr ,x ;execute the sub on the stack 1156 ff95 a7 1b i_cont: ais #spsubsize+3 ;deallocate sub body + h:x + command 1157 ;h:x flash pointer ok from spsub 1158 ff97 48 lsla ;a=00 & z=1 unless pviol or accerr 1159 ff98 81 rts ;to flash where doonstack was called f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d doonstack subroutine serial monitor for mc9s08gb/gt 17 although spsub appears to be located at $ff99?$ffb0, during execution we actually execute a copy of spsub that is temporarily located on the stack in ram. spsub completes the flash command by performing the following steps: 1. write to a flash location. the data for this write was in a when spsub was started. the address was previously stored on the stack and is loaded into h:x with a stack-pointer-relative ldhx instruction at line 1175. 2. write the code for byte_prog or page_erase to the fcmd register. the command code is also retrieved from the stack with a stack-pointer-relative load instruction. 3. write a 1 to fcbef to initiate the command. 4. wait for fccf = 1 to indicate the operation is complete and the flash is again visible in the normal memory map. the nop in line 1181 is used to ensure that there are at least four cycles between the write to fcbef (line 1180) and the first read of fstat (line 1182). this delay is required so the internal flash command sequencer can properly update the fcbef and fccf flags in fstat. execution stays in the chkdone loop until the command finishes (fccf becomes set). at this point the flash is back in the memory map and we can return to doonstack (which is in the flash). 1175 ff99 9efe 1c spsub: ldhx AN2140/d stack usage details serial monitor for mc9s08gb/gt 19 $fff4?$fffd. in the special case of the icg vector, this verification routine only checks to make sure the icg vector is not blank. if a user has already programmed a vector for a user-supplied icg isr, this routine accepts that vector. if the icg vector location is unprogrammed ($ffff), the verification routine programs a default vector to a simple isr in the monitor. stack usage details worst case stack usage by the monitor determines how much extra space a user must allow below the application stack to support debugging with the monitor. typically, the functions for programming and erasing nonvolatile memory are done before attempting to do any debugging on user programs. because of this, the amount of stack needed for these commands is generally not important. the monitor was written to try to minimize the amount of stack needed to support debugging. during reset initialization, the stack pointer is set to the end of ram ($107f in the mc9s08gb60) and a 6-byte user register stack frame is set up with all 0s except the user ccr which is initially set to $68 (i bit = 1) and the user pc which is initially loaded with the user?s reset vector from $fbfe:fbff. an additional two bytes of stack are used while printing the prompt sequence. this is a worst case stack depth of eight bytes before processing any commands. while waiting for new commands, the stack is eight bytes deep ? six bytes for the user register stack frame and two bytes for the jsr to the getchar routine. when nonvolatile memory is not being programmed, monitor commands use up to 17 bytes of stack space including the 6 bytes used for the user register stack frame. if a write_byte or write_next command is used to program a flash byte, 45 bytes of stack are used including the 6 bytes for the user register stack frame. if a write_block command is used to program a flash byte, 47 bytes of stack are used including the 6 bytes for the user register stack frame. the reset command does not use any extra stack except the six bytes for the user register stack frame and the two bytes for jsr getchar. the erase commands use 50 bytes including the 6 bytes for the user register stack frame. the bottom line for worst case stack usage is that an application should allot 50 bytes of extra stack space in their application programs to allow for debugging with the monitor program. if no nonvolatile memory needs to be programmed, only 17 bytes of extra stack space are needed. failure to allow for this extra space could result in the monitor overwriting other user resources such as ram variables or registers. for applications that cannot tolerate this extra stack space, use a bdm-based debug pod which does not need any user memory or i/o resources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 20 serial monitor for mc9s08gb/gt the monitor checks the value of sp in the swi service routine to make sure it can support normal monitor activity. if sp is less than ramstart+$45 or greater than ramlast, the monitor forces a warm reset to get the stack pointer back into a legal range. if sp is outside this range, the stacking operation for the swi could have written over other system resources including program variables or control and status registers.the lower limit (ramstart+$45) could have been set at ramstart+50, but some guard band was allowed in case changes are made to the monitor program some time in the future. tricks to save code space this section describes several techniques that were used to reduce code space. some of these techniques are good programming practices while others should only be used as a last resort. this 1-kbyte monitor is compact and is usually used without modification so a few unusual tricks were used to make the code fit within a 1-kbyte protected block. care was taken to document these techniques to avoid future problems when this program is modified for other hcs08 derivatives. utility subroutines one of the most common ways to reduce code space is to develop a good set of utility subroutines. a good utility subroutine is one that can be used in several different contexts to perform some common task. a few obvious choices are getchar and putchar routines to receive and send characters through the sci serial interface. other utility routines that were used in this bootloader are pcrlf, printcrlf, printmsg, and writea2hx. partition common blocks of code into subroutines this technique is similar to the idea of making utility subroutines except that these blocks of code are not as general purpose as something like the getchar routine. the usual way these sequences are detected is that a programmer will notice they are doing something very similar in two or more places in a program. when this happens, they can study the code and try to make a subroutine out of the common parts of the sequence. one example of this technique is the preinc subroutine which is used in the write_next and read_next commands. in both of these commands, the user?s h:x register must be retrieved from the user register stack frame, get incremented by one, and be updated in the user register stack frame. the incremented h:x value must be in the h:x register to perform the requested read or write operation. the common subroutine saved 10 bytes of code space compared to doing a 5-line in-line sequence twice. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d user-accessible utility subroutines serial monitor for mc9s08gb/gt 21 other examples of this technique in the monitor include doonstack, and writea2hx. these routines are discussed in more detail elsewhere in this application note. writea2hx subroutine the writea2hx subroutine saves code space similar to the way other subroutines save space, but there is another, more important result from combining this function into a subroutine. the write_byte command, the write_next command, and the write_block command all change the contents of memory locations. by building this function into a subroutine, it was possible to make the operation smart so that it could use the address to intelligently decide whether to program flash memory or simply write the data to the requested ram or register location. the routine also performs error checks to detect improper attempts to program nonvolatile locations. the resulting routine ensures that flash programming will be performed in exactly the same way no matter which monitor command is responsible for the change. this helps improve code reliability and reduces the amount of testing for the final program. if a change is needed for the nonvolatile programming algorithm, it can be changed in this one routine rather than having to locate three different places to correct the program. user-accessible utility subroutines this monitor includes two user-accessible utility subroutines that can be called through a jump table. the jump table is located in the first 6 bytes of the 1-kbyte protected monitor memory. the jump table provides a way to call these routines at a predictable address that doesn?t change even if the monitor program is changed so that the actual subroutines are located at different addresses. for example, when a user program executes a jsr to uprg1flash (at $fc00), the jmp instruction at $fc00 passes control to the actual prg1flash subroutine wherever it happens to be located in the 1-kbyte monitor program. the two utility routines are: uprg1flash($fc00) ? writes the value in accumulator a to the address pointed to by h:x. if the z condition code is set (.eq.) after returning from this subroutine, it indicates the operation was successful. if z is clear (.ne.), it indicates an faccerr or fpviol error was detected during an attempted flash programming operation, or the flash location that was being written had some bits already programmed before the programming operation was attempted. uerasepages ($fc03) ? erases one or more 512-byte pages of flash memory. before calling this subroutine, push the end address onto the stack and load h:x with the start address for the range of locations you want to erase. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 22 serial monitor for mc9s08gb/gt if the operation is successful, the z bit is set on return from this subroutine. if the range of addresses is not within the unprotected portion of the flash, or if there is an faccerr or fpviol error during the erase operation, the z bit will be cleared on return. for additional information about the detailed operation of the utility subroutines, refer to the complete listing for the monitor program. modifications for clock speed and memory map variations this section describes the changes that would be needed to adapt this monitor to another mc9s08gb60 system that uses a different frequency source such as a 4-mhz crystal. for other hcs08 devices, refer to the specific data sheet for detail about where to make similar changes. there are several frequency-related dividers that would need to be adjusted. in the most extreme case, this monitor may be adapted to some new hcs08 derivative that has a different type of clock generator module. in the case of a different clock generator, you would need to change the initialization code in lines 402 through 408. most other changes can be made by simply adjusting some of the initialization constants at the top of the program. setting bus frequency the first change for a different frequency source would be to adjust the settings in initicgc1 and initicgc2. refer to the device data sheet for detailed information about how these registers should be set up. icgc1 includes settings for: range selects the crystal frequency range (for example, low range for 32-khz crystals or internal self-clocked frequency source and high range for a 4-mhz crystal) setting refs to 1 enables the crystal oscillator amplifier if a crystal will be used; refs can be set to 0 if the internal self-clocked reference will be used. the clks1:clks0 bits select the fll operating mode which should be fee for a crystal or fei for the internal self-clocked oscillator. if the internal self-clocked frequency source is used, you should also adjust the trim in the icgtrm register to establish a relatively accurate 243-khz frequency source. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d modifications for clock speed and memory map variations serial monitor for mc9s08gb/gt 23 icgc2 is used to set the fll dividers to multiply the source frequency to get the icgout frequency, which is 2x the bus frequency. the mfd control field sets a multiplier factor n. the rfd field sets a post fll divider. when the internal self-clocked frequency source is used, the source frequency for these calculations is (243 khz / 7). the overall relationship between source frequency and bus frequency is: for a low frequency crystal source such as 32.768 khz (range = 0, refs = 1, clks = 1:1 in icgc1) for this monitor set icgc1 = %00111000 source_frequency * 64 * (n / 2r) = bus_frequency ex. 32.768 khz * 64 * (18 / 2) = 18.874368 mhz where... n = 18 (mfd = 1:1:1) and r = 1 (rfd = 0:0:0) for this monitor set icgc2 = %01110000 for the internal self-clocked frequency source (range = refs = 0, clks = 0:1 in icgc1) for this monitor set icgc1 = %00001000 source_frequency * 64 * (n / 2r) = bus_frequency ex. (243 khz / 7) * 64 * (18 / 2) = 19.995427 mhz where... n = 18 (mfd = 1:1:1) and r = 1 (rfd = 0:0:0) for this monitor set icgc2 = %01110000 for a high frequency crystal source such as 4 mhz (range = 1, refs = 1, clks = 1:1 in icgc1) for this monitor set icgc1 = %01111000 source_frequency * 1 * (n / 2r) = bus_frequency ex. 4 mhz * 1 * (10 / 2) = 20 mhz where... n = 10 (mfd = 0:1:1) and r = 1 (rfd = 0:0:0) for this monitor set icgc2 = %00110000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 24 serial monitor for mc9s08gb/gt setting up sci baud rate sci baud rates are derived by dividing the bus frequency, so if the bus frequency changes, the divider for the baud rate generator must change. this monitor uses 115.2 kbaud (for the mc9s08gb60). some other variations of this monitor for hcs08 devices that operate from a slower clock source may use slower baud rates. for reliable sci communications, the baud rate must be within about 4.5% of the ideal rate. a modulo divider is controlled by the sbr (sbr12..sbr0) setting in the sci1bdh and sci1bdl registers. since this program does not use any divisor that is greater than 8 bits, the sci1bdh register can be left at its default $00 value and all baud rate adjustment will be done using the sci1bdl register. when sbr = 0, the baud rate generator is off. the formula for computing baud rate from bus frequency is baud_rate = bus_frequency / (sbr * 16) the following table summarizes the bus frequency, sbr settings, and frequency tolerance for 9600 baud and 115.2 kbaud for this monitor assuming a 32.768 khz crystal, a 4 mhz crystal, or the internal self-clocked frequency source. bus frequency values assume the fll settings shown in setting bus frequency . setting longbreak constant this monitor sends a break to the host pc to get its attention when the target system is powered up. because some windows-based pcs need a long period of break to detect the condition, this monitor sends a break that is about 30 bit-times at the selected baud rate. this time delay is not critical, but it should be at least 30 bit-times. the monitor generates this break delay time by executing a software loop that is eight bus cycles long. the number of times this loop is executed is set by the table 1. baud rate setup frequency source bus frequency (mhz) sbr baud rate (baud) frequency tolerance 32.768 khz 18.874368 123 9600 ?0.1% 32.768 khz 18.874368 10 115.2 k +2.4% 4 mhz 20 130 9600 +1.6% 4 mhz 20 11 115.2 k +1.36% (internal) 19.995427 129 9600 +0.9% (internal) 19.995427 11 115.2 k +1.4% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d modifications for clock speed and memory map variations serial monitor for mc9s08gb/gt 25 value in longbreak. one bit-time is equal to 16 times the baud rate constant. to get the number of loops to execute for 32 bit-times (for example), you would take (the baud rate constant) * 16 * 32 / 8. to compute the value for longbreak to get a 30 to 32 bit-time break, multiply the baud rate constant first by 60 and then 64, and then choose a convenient number between these two values. for a 32.768 khz-based system with bus speed 18.874368 mhz, longbreak is set to 625. for a 4 mhz-based system with bus speed 20 mhz, longbreak is set to 700. in a system that uses the internal frequency source and a bus speed of 19.995427 mhz, set longbreak to 700. flash system clock speed the flash memory system uses an internal state machine to execute programming and erase commands. the timing of these commands is determined by the speed of a clock in the flash module and this clock must be between 150 khz and 200 khz for proper operation. the flash clock (fclk) speed is bus_frequency / (8 * (fcdiv + 1)) = fclk memory map changes most changes to the memory map from one hcs08 derivative to another will be taken into account automatically by replacing the 9s08gb60_v1.equ file with the equate file for the appropriate derivative mcu. this file specifies the start and end address locations for the ram and flash memory and for all status and control registers. you may wish to change the port pins for the switch that forces monitor versus user mode (pta7 in the initial version for the mc9s08gb60), and for the sci rxd pin. these changes can be made by modifying the equate directives at the beginning of the monitor program. table 2. fcdiv settings frequency source bus frequency fcdiv fclk 32.768 khz 18.874368 mhz 11 196.608 khz 4 mhz 20 mhz 12 192.308 khz (internal) 19.995427 mhz 12 192.264 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d 26 serial monitor for mc9s08gb/gt conclusion this application note has described a 1-kbyte serial monitor program. in addition to functioning as a debug monitor program, the serial monitor program serves as a good programming example for the hcs08 family of microcontrollers and demonstrates a number of useful programming techniques. routines for erasing and programming nonvolatile flash memory are described in detail. the unusual doonstack subroutine copies a routine onto the stack and executes it there since it is not possible to program or erase the flash memory from code executing within the same flash. this routine can easily be adapted for use in other user programs. the writea2hx subroutine decides whether to use flash or simple ram write operations, depending on the address of the location to be programmed. the reset initialization routines show how to setup the fll and sci subsystems. a technique for differentiating between a warm reset compared to a cold reset is also described. a set of 19 primitive monitor commands support third-party flash programming and debug tools. this monitor allows for debugging through an on-chip sci serial interface instead of using a more expensive background debug interface pod. vector redirection through a new hardware mechanism is described, and techniques to reduce code size are discussed. code listing two zip files accompany this application note, AN2140sw1.zip and AN2140sw2.zip. AN2140sw1.zip contains just the assembly files for both the 32-khz crystal and 4-mhz crystal versions of the serial monitor program along with the necessary equate file. this zip file does not contain compiled versions of the programs. AN2140sw2.zip contains two complete project folders, one for each version of the serial monitor program. these project directories are for use with metrowerks codewarrior for cw08_v3.0. the folders are named ?32k_9s08gb60_monitor? and ?4m_9s08gb60_monitor.? inside the first level of each project folder is a codewarrior project file with a ?.mcp? filename extension. double clicking these files will open the project if codewarrior has been installed. each project has been assembled and listings (?.lst? file extension) are available in the ?bin? subfolders. also, the s records (?.s19? file extension) are available in the same folder. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d code listing serial monitor for mc9s08gb/gt 27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . AN2140/d rev. 1 6/2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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